This invention relates to a semiconductor integrated circuit (IC) operable as a semiconductor decoding device which comprises a plurality of MOS (metal-oxide semiconductor) field-effect transistors (FETS). Such a semiconductor decoding device is used, for example, as an address decoder for use in combination with a memory device.
In the manner known in the art, a semiconductor decoding device has a first plurality of device input terminals and a second plurality of device output terminals. When the first plurality is equal to three, the second plurality is equal to eight or less.
The device input terminals are supplied with a plurality of binary device input signals, equal in number to the first plurality. From time to time, the device input signals are variable between first and second input levels, such as binary one and binary zero input levels, independently of one another. The device input signals therefore have an input level combination of the first and the second input levels at any given time. It should be noted in this connection that the combination may be given either by the device input signals having the first input level alone in common or by the device input signals having the second input level alone in common.
In a specific case, the semiconductor decoding device may have a predetermined plurality of device input terminals and only one device output terminal. In this event, the input level combination should become a predetermined combination of the first and the second input levels during a certain time interval. The semiconductor decoding device decodes the first and the second input levels of the predetermined combination into a decoded level for supply to the device output terminal with a decoded signal having the decoded level as a device output signal during the time interval under consideration.
In the manner which will later be described in detail, a conventional semiconductor decoding device comprises a parallel circuit of a plurality of MOS field effect transistors of a predetermined conductivity type, such as an n-channel type, equal in number to the predetermined plurality. The parallel circuit is connected to the output terminal. A signal supply section is connected to the parallel circuit for supplying the device input signals to the respective (MOS) field effect transistors. A load circuit is connected to the output terminal and consequently to the parallel circuit. A power supply section is connected to the load circuit for supplying electric power to the load circuit.
In such a semiconductor decoding device, the load circuit has an active and an inactive state. When put in the active state during a first time interval, the load circuit supplies the electric power to the parallel circuit and to the device output terminal. When put in the inactive state during a second time interval, the load circuit inhibits supply of the electric power to each of the parallel circuit and the device output terminal. The device output signal of the decoded level is produced when the load circuit is put in the active state in the time interval in which the device input signals have the predetermined combination of the first and the second input levels.
In the semiconductor decoding device of this kind, the output terminal is charged by the electric power through the load circuit put in the active state. This makes the device output signal have a binary one output level, which may serve as the decoded level. When it is desired to give a binary zero output level to the device output signal, the device output terminal must be discharged.
In order to discharge the device output terminal, the conventional semiconductor decoding device comprises a plurality of NOR gates, equal in number to twice the above-mentioned first plurality even when the second plurality is equal to a half of a three-term algebraic sum of the first plurality square minus the first plurality plus two. As a result, the conventional semiconductor device has a degraded degree of integration. In addition, charge/discharge must be repeated at a cycle composed of the first and the second time intervals. This results in an objectionably great current consumption.